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package br.unioeste.cc.vm;

/**
 *
 * @author diego
 */
public class UnitControl {

    int opCode, branch;
    int regDst, aluSrc;
    int memToReg;
    int memRead, memWrite;
    int regWrite;
    int aluOp;
    int bne, lui;
    int jump, jr;
    int funct;

    public int getFunct() {
        return funct;
    }

    public void setFunct(int funct) {
        this.funct = funct;
    }

    public int getBne() {
        return bne;
    }

    public void setBne(int bne) {
        this.bne = bne;
    }

    public int getLui() {
        return lui;
    }

    public void setLui(int lui) {
        this.lui = lui;
    }

    public int getRegWrite() {
        return regWrite;
    }

    public void setRegWrite(int regWrite) {
        this.regWrite = regWrite;
    }

    public int getAluOp() {
        return aluOp;
    }

    public void setAluOp(int aluOp) {
        this.aluOp = aluOp;
    }

    public int getAluSrc() {
        return aluSrc;
    }

    public void setAluSrc(int aluSrc) {
        this.aluSrc = aluSrc;
    }

    public int getBranch() {
        return branch;
    }

    public void setBranch(int branch) {
        this.branch = branch;
    }

    public int getMemRead() {
        return memRead;
    }

    public void setMemRead(int memRead) {
        this.memRead = memRead;
    }

    public int getMemToReg() {
        return memToReg;
    }

    public void setMemToReg(int memToReg) {
        this.memToReg = memToReg;
    }

    public int getMemWrite() {
        return memWrite;
    }

    public void setMemWrite(int memWrite) {
        this.memWrite = memWrite;
    }

    public int getOpCode() {
        return opCode;
    }

    public void setOpCode(int opCode) {
        this.opCode = opCode;
    }

    public int getRegDst() {
        return regDst;
    }

    public void setRegDst(int regDst) {
        this.regDst = regDst;
    }

    /**
     * gera os sinais de controle
     */
    public void signalControl() {
        switch (opCode) {
            case 0: //type-R
                if (funct == 8) {//jr 
                    regDst = 0;
                    aluSrc = 0;
                    memToReg = 0;
                    regWrite = 0;
                    memRead = 0;
                    memWrite = 0;
                    branch = 0;
                    aluOp = 0;
                    bne = 0;
                    lui = 0;
                    jump = 1;
                    jr = 1;
                } else {
                    regDst = 1;
                    aluSrc = 0;
                    memToReg = 0;
                    regWrite = 1;
                    memRead = 0;
                    memWrite = 0;
                    branch = 0;
                    aluOp = 2;
                    bne = 0;
                    lui = 0;
                    jump = 0;
                    jr = 0;
//                System.out.println("Sinais de Controle: \n");
//                System.out.println("regDst = " + regDst);
//                System.out.println("aluSrc = " + aluSrc);
//                System.out.println("memToReg = " + memToReg);
//                System.out.println("regWrite = " + regWrite);
//                System.out.println("memRead = " + memRead);
//                System.out.println("memWrite = " + memWrite);
//                System.out.println("branch = " + branch);
//                System.out.println("aluOp = " + aluOp);
                }
                break;
            case 2: //jump
                regDst = 0;
                aluSrc = 0;
                memToReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 0;
                bne = 0;
                lui = 0;
                jump = 1;
                jr = 0;
                break;
            case 4: //beq 
                regDst = 0;
                aluSrc = 0;
                memToReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 1;
                aluOp = 1;
                bne = 0;
                lui = 0;
                jump = 0;
                jr = 0;
                break;
            case 5://bne 
                regDst = 0;
                aluSrc = 0;
                memToReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 1;
                aluOp = 1;
                bne = 1;
                lui = 0;
                jump = 0;
                jr = 0;
                break;
            case 15://lui
                regDst = 0;
                aluSrc = 0;
                memToReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 0;
                bne = 0;
                lui = 1;
                jump = 0;
                jr = 0;
                break;
            case 35: //lw
                regDst = 0;
                aluSrc = 1;
                memToReg = 1;
                regWrite = 1;
                memRead = 1;
                memWrite = 0;
                branch = 0;
                aluOp = 0;
                bne = 0;
                lui = 0;
                jump = 0;
                jr = 0;
            case 43: //sw
                regDst = 0;
                aluSrc = 1;
                memToReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 1;
                branch = 0;
                aluOp = 0;
                bne = 0;
                lui = 0;
                jump = 0;
                jr = 0;
            default:
                break;
        }
    }
}